The present invention relates to transistors, and more specifically, to field effect transistors formed with graphene channels.
Graphene is a one-atom-thick planar sheet of sp2-bonded carbon atoms that are densely packed in a honeycomb crystal lattice. It can be viewed as an atomic-scale chicken wire made of carbon atoms and their bonds.
Graphene possesses great potential for high-speed electronics because of its high carrier mobility and the ultra-thin single atom body thickness. In addition to the carrier mobility, the performance of a transistor also depends on the parasitic capacitance and resistance associated with its terminals. The impact of these parasitic capacitances on device performance becomes particularly important with the shrinking of device dimensions. In order to minimize the parasitic capacitance between source/drain and gate electrodes, it is necessary to maintain a device structure where the gate electrode lies between the source/drain electrodes without overlaps. However, this gap (the un-gated region between source/drain and the gate) gives rise to an access resistance, and contributes to the overall drain-to-channel and source-to-channel parasitic resistances. Therefore, the most desirable transistor structure is a self-aligned device where the gate and the source/drain electrodes align to each other without overlaps and with minimum gaps.
In silicon (Si) MOSFETs, self-aligned FETs are usually realized by forming an oxide side-wall surrounding the gate stack before the formation of source/drain contacts. However, this technique cannot be directly applied in the case of graphene due to the differences in material processing requirements between Si and carbon. Currently, there is no scheme known to fabricate such self-aligned graphene transistors.